A big problem in dense PCB layout is crosstalk between traces.
Purely analog and mixed analog/digital boards are more prone to this, especially when the audio path is expected to be clean and free of noise. In a pure analog board, you might see a signal from one channel on a different channel, faintly in the background, or you might not be able to turn a signal all the way down/off like the circuit was designed to do. In a mixed signal board, you might hear a periodic ticking sound when a microcontroller updates an LED or reads from an external memory chip, or you might see an ADC value change on one channel when you turn the knob of another channel.
There could be many causes for these problems, but in this article I’d like to discuss one such cause: parallel traces. Other problems (each of which deserves an article to itself) could be poorly designed ground/return paths, inadequate power regulation, use of chips with poor PSRR (combined with inadequate regulation), etc.
Parallel traces on the board act like capacitors and signals you routed along one trace can “mysteriously” appear in another trace. Since capacitors conduct higher frequencies more easily than lower frequencies, a indicator that you might be dealing with trace-to-trace crosstalk is if higher frequencies are bleeding more readily than lower frequencies. This doesn’t prove that the path of the bleed is trace-to-trace capacitance, but it’s worth investigating!
For example, let’s say we have a simple four channel analog mixer. Let’s say we’re testing our first prototype and we find that a 10kHz sine wave fed into channel 1 can be heard on the main output even when channel 1’s level pot is turned down to 0. However, a 500Hz sine wave of the same amplitude isn’t heard at all. Further investigation shows that the 10kHz bleed can be controlled by channel 2’s level pot. Aha! We now should take a look at our board layout and look for traces that carry channel 1’s signal (before the level pot attenuates it) that are near traces carrying channel 2’s signal (also before the level pot attenuates it).
Let’s say we found two traces that might be causing the bleed. How do we find out for sure if this is the cause of the problem?
Do the math!
The formula for Capacitance between two traces is:
C = e0 * eR * t * (L/d)
e0 is a constant (the permittivity in a vacuum), and eR is another constant determined by the PCB material
t is the thickness of the trace
L is the length of the parallel section
d is the separation between the traces
In a typical board, the material is FR4 and the traces are 0.003mm (0.12mil).
e0 = 8.84 pF/m
eR = 4.7 (roughly)
t = 0.003mm = 0.12mil
Since all these are constant, we can multiply them together and simplify our equation like this:
e0 * eR * t = 0.000125pF
C = 0.000125pF * (L/d)
Back to our example, if our traces were 6mil apart, and parallel to each other for a distance of 600mil:
C = 0.000125pF * 600mil/6mil = 0.0125pF
So it’s essentially like we soldered a 0.01pF capacitor between those two traces.
How much bleed could that cause?
I = C * dV/dt
where dV/dt is the rate of change of the voltage, which is essentially amplitude * 2 * frequency of an analog sine wave, or rise time of a square wave
So for a 10kHz sine wave of 10V amplitude, we have a dV = 10V and dt = 1/(10kHz * 2) . We multiply the frequency by 2 because in a sine wave the voltage changes by 10V twice for every period (once rising and once falling).
dV/dt = 10V / (1/20kHz) = 10V/50us = 1V/5us = 0.2V/us
So the induced current would be
I = C * 0.2V/us = 0.01pF * 0.2V/us = 0.002V pF/us = 2nA
Hmm, 2nA doesn’t sound like much, does it? Well… let’s say the receiving trace is an input to a JFET opamp. The impedance could be around 100Mohms,. The induced voltage will be:
V = I * R
V = 2nA * 100Mohms = 200mV = 0.2V
And that’s quite audible!